This invention relates to an electronic packaging and interconnection of a contact structure, and more particularly, to an electronic packaging and interconnection for mounting a contact structure on a probe card or equivalent thereof which is used to test semiconductor wafers, semiconductor chips, packaged semiconductor devices or printed circuit boards and the like with increased accuracy, density and speed.
In testing high density and high speed electrical devices such as LSI and VLSI circuits, high performance probe contactors or test contactors must be used. The electronic packaging and interconnection of a contact structure of the present invention is directed to the application of testing and burn-in testing of semiconductor wafers and dies, but not limited to such applications and is inclusive of testing and burn-in test of packaged semiconductor devices, printed circuit boards and the like. However, for the convenience of explanation, the present invention is described in the following mainly with reference to a probe card to be used in semiconductor wafer testing.
In the case where semiconductor devices to be tested are in the form of a semiconductor wafer, a semiconductor test system such as an IC tester is usually connected to a substrate handler, such as an automatic wafer prober, to automatically test the semiconductor wafer. Such an example is shown in FIG. 1 in which a semiconductor test system has a test head 100 which is ordinarily in a separate housing and electrically connected to the test system through a bundle of cables. The test head 100 and the substrate handler 400 are mechanically connected with one another by means of a manipulator 500 and a drive motor 510 shown in FIG. 1. The semiconductor wafers to be tested are automatically provided to a test position of the test head by the substrate handler such as a wafer prober.
On the test head, the semiconductor wafer to be tested is provided with test signals generated by the semiconductor test system. The resultant output signals from the semiconductor wafer under test are transmitted to the semiconductor test system wherein they are compared with expected data to determine whether IC circuits (chips) on the semiconductor wafer function correctly or not.
As shown in FIGS. 1 and 2, a test head 100 and a substrate handler 400 are connected with each other through an interface component 140. The interface component 140 includes a performance board 120 which is typically a printed circuit board having electric circuit connections unique to a test head""s electrical footprint, such as coaxial cables, pogo-pins and connectors. The test head 100 includes a large number of printed circuit boards 150 which correspond to the number of test channels (tester pins) of the semiconductor test system. Each of the printed circuit boards 150 has a connector 160 to receive therein a corresponding contact terminal 121 of the performance board 120.
In the example of FIG. 2, a xe2x80x9cfrogxe2x80x9d ring 130 is mounted on the performance board 120 to accurately determine the contact positions relative to the substrate handler 400 such as a wafer prober. The frog ring 130 has a large number of contact pins 141 formed, for example, by ZIF connectors or pogo-pins, connected to the contact terminals 121, through coaxial cables 124.
FIG. 2 further shows a structural relationship between the substrate handler 400, the test head 100 and the interface component 140 when testing a semiconductor wafer. As shown in FIG. 2, the test head 100 is placed over the substrate handler 400 and mechanically and electrically connected to the substrate handler through the interface component 140. In the substrate handler 400, a semiconductor wafer 300 to be tested is mounted on a chuck 180. A probe card 170 is provided above the semiconductor wafer 300 to be tested. The probe card 170 has a large number of probe contactors (contact structures) 190, such as cantilevers or needles, to contact with circuit terminals or contact targets or contact pads in the IC circuit of the semiconductor wafer 300 under test.
Electrical terminals or contact receptacles of the probe card 170 are electrically connected to the contact pins 141 provided on the frog ring 130. The contact pins 141 are also connected to the contact terminals 121 of the performance board 120 via the coaxial cables 124 where each contact terminal 121 is connected to the printed circuit board 150 of the test head 100. Further, the printed circuit boards 150 are connected to the semiconductor test system main frame through the cable bundle 110 having several hundreds of cables therein.
Under this arrangement, the probe contactors (needles or cantilevers) 190 contact the surface of the semiconductor wafer 300 on the chuck 180 to apply test signals to the IC chips on the semiconductor wafer 300 and receive the resultant signals of the IC chips from the wafer 300. The resultant output signals from the semiconductor wafer 300 under test are compared with the expected data generated by the semiconductor test system to determine whether the IC chips in the semiconductor wafer 300 properly perform the intended functions.
FIG. 3 is a bottom view of the probe card 170 of FIG. 2. In this example, the probe card 170 has an epoxy ring on which a plurality of probe contactors 190 called needles or cantilevers are mounted. When the chuck 180 mounting the semiconductor wafer 300 moves upward in FIG. 2, the tips of the cantilevers 190 contact the contact targets such as contact pads or bumps on the wafer 300. The ends of the cantilevers 190 are connected to wires 194 which are further connected to transmission lines (not shown) formed in the probe card 170. The transmission lines in the probe card 170 are connected to a plurality of electrodes 197 which further contact the pogo pins 141 of FIG. 2.
Typically, the probe card 170 is structured by a multi-layer of polyimide substrates having ground planes, power planes, signal transmission lines in many layers. As is well known in the art, each of the signal transmission lines is designed to have a characteristic impedance such as 50 ohms by balancing the distributed parameters, i.e., dielectric constant and magnetic permeability of the polyimide, inductances and capacitances of the signal paths within the probe card 170. Thus, the signal transmission lines are impedance matched to achieve a high frequency transmission bandwidth to the wafer 300 under test. The signal transmission lines transmit a small current during a steady state of a pulse signal and a large peak current during a transition state of the device""s outputs switching. For removing noise, capacitors 193 and 195 are provided on the probe card 170 between the power and ground planes.
An equivalent circuit of the probe card 170 is shown in FIGS. 4A-4E to explain the limitations of bandwidth in the conventional probe card technology. As shown in FIGS. 4A and 4B, the signal transmission line on the probe card 170 extends from the electrode 197, the strip line (impedance matched line) 196, the wire 194 and the needle (cantilever) 190. Since the wire 194 and needle 190 are not impedance matched, these portions function as an inductor L in the high frequency band as shown in FIG. 4C. Because of the overall length of the wire 194 and needle 190 is around 20-30 mm, the value of the inductor L is not trivial, resulting in the significant frequency limitation in testing a high frequency performance of a device under test.
Other factors which limit the frequency bandwidth in the probe card 170 reside in both power and ground needles shown in FIGS. 4D and 4E. If a power line can provide large enough currents to the device under test, it will not seriously limit the operational bandwidth in testing the device. However, because the series connected wire 194 and needle 190 for supplying the power to the device under test are equivalent to the inductors as shown in FIG. 4D, which impede the high speed current flow in the power line. Similarly, because the series connected wire 194 and needle 190 for grounding the power and signals are equivalent to the inductors as shown in FIG. 4E, the high speed current flow is impeded by the wire 194 and needle 190.
Moreover, the capacitors 193 and 195 are provided between the power line and the ground line to secure a proper performance of the device under test by filtering out the noise or surge pulses on the power lines. The capacitors 193 have a relatively large value such as 10 xcexcF and can be disconnected from the power lines by switches if necessary. The capacitors 195 have a relatively small capacitance value such as 0.01 xcexcF and fixedly connected close to the DUT (device under test). Since these capacitors serve as high frequency decoupling on the power lines, which also impede the high speed current flow in the signal and power lines.
Accordingly, the probe contactors noted above are limited to the frequency bandwidth of approximately 200 MHz which is insufficient to test recent semiconductor devices. It is considered, in the industry, that the frequency bandwidth equal to the tester""s capability, which is currently on the order of 1 GHz or higher, will be necessary in the near future. Further, it is desired in the industry that a probe card is capable of handling a large number of semiconductor devices, especially memory devices, such as 32 or more, in a parallel fashion at the same time to increase test throughput.
To meet the next generation test requirements noted above, the inventors of this application has provided a new concept of contact structure in the U.S. application Ser. No. 09/099,614 xe2x80x9cprobe Contactor Formed by Photolithography Processxe2x80x9d filed Jun. 19, 1998. The contact structure is formed on a silicon or dielectric substrate through a photolithography process. FIGS. 5 and 6A-6C show the contact structure in the above noted application. In FIG. 5, all of the contact structures 30 are formed on a silicon substrate 20 through the same photolithography process. The silicon substrate 20 having the contact structures 30 may be mounted on a probe card such as shown in FIGS. 2 and 3. When the semiconductor wafer 300 under test moves upward, the contact structures 30 contact with corresponding contact targets (electrodes or pads) 320 on the wafer 300.
The contact structure 30 on the silicon substrate 20 can be directly mounted on a probe card such as shown in FIG. 3, or molded in a package, such as a traditional IC package having leads, so that the package is mounted on a probe card. In the above noted patent application by the inventors, such technologies of packaging and interconnection of the contact structure 30 with respect to the probe card or equivalent thereof is not described.
Therefore, it is an object of the present invention to provide a packaging and interconnection of a contact structure with respect to a probe card or equivalent thereof to be used in testing a semiconductor wafer, packaged LSI and the like.
It is another object of the present invention to provide a packaging and interconnection of a contact structure with respect to a probe card or equivalent thereof to achieve a high speed and high frequency operation in testing a semiconductor wafer, packaged LSI and the like.
It is a further object of the present invention to provide a packaging and interconnection of a contact structure with respect to a probe card or equivalent thereof wherein the packaging and interconnection is formed at a bottom surface of the substrate mounting the contact structure.
It is a further object of the present invention to provide a packaging and interconnection of a contact structure which is established through a bonding wire, a single layer tape automated bonding (TAB), or a multi-layer tape automated bonding (TAB) at the bottom surface of the substrate mounting the contact structure.
It is a further object of the present invention to provide a packaging and interconnection of a contact structure which is established between a contact pad formed at the bottom surface of the substrate mounting the contact structure and an electric connector.
It is a further object of the present invention to provide a packaging and interconnection of a contact structure which is established between a contact pad formed at the bottom surface of the substrate mounting the contact structure and an interconnect pad of a printed circuit board through a solder bump.
It is a further object of the present invention to provide a packaging and interconnection of a contact structure which is established between a contact pad formed at the bottom surface of the substrate mounting the contact structure and an interconnect pad of a printed circuit board through a conductive polymer.
In the present invention, an electronic packaging and interconnection of a contact structure to be used in a probe card or equivalent thereof to test semiconductor wafers, semiconductor chips, packaged semiconductor devices or printed circuit boards and the like is established between a contact pad formed at the bottom surface of the substrate mounting the contact structure and various types of connection means on the probe card. The contact pad at the bottom is connected to the contact structure at an upper surface of the substrate through a via hole and a contact trace both of which are provided on the substrate.
In one aspect of the present invention, a packaging and interconnection of a contact structure is comprised of: a contact structure made of conductive material and formed on a contact substrate through a photolithography process wherein the contact structure has a base portion vertically formed on the contact substrate, a horizontal portion, one end of which being formed on the base portion, and a contact portion vertically formed on another end of the horizontal portion; a contact pad formed on a bottom surface of the contact substrate and electrically connected to the contact structure through a via hole and a contact trace; a contact target provided on a printed circuit board (PCB) substrate to be electrically connected with the contact pad on the contact substrate through a conductive bump or polymer.
In another aspect of the present invention, a packaging and interconnection of a contact structure is comprised of: a contact structure made of conductive material and formed on a contact substrate through a photolithography process wherein the contact structure has a base portion vertically formed on the contact substrate, a horizontal portion, one end of which being formed on the base portion, and a contact portion vertically formed on another end of the horizontal portion; a contact pad formed on a bottom surface of the contact substrate and electrically connected to the contact structure through a via hole and a contact trace; a contact target provided on a printed circuit board (PCB) substrate or lead frame to be electrically connected with the contact pad on the contact substrate through a bonding wire; and a support structure for supporting the contact structure and the contact substrate.
In a further aspect of the present invention, a packaging and interconnection of a contact structure is comprised of: a contact structure made of conductive material and formed on a contact substrate through a photolithography process wherein the contact structure has a base portion vertically formed on the contact substrate, a horizontal portion, one end of which being formed on the base portion, and a contact portion vertically formed on another end of the horizontal portion; a contact pad formed on a bottom surface of the contact substrate and electrically connected to the contact structure through a via hole and a contact trace; a contact target provided on a printed circuit board (PCB) substrate or lead frame to be electrically connected with the contact pad on the contact substrate through a tape automated bonding (TAB) lead; an elastomer provided under the contact substrate for allowing flexibility in the interconnection and packaging; and a support structure for supporting the contact structure, the contact substrate and the elastomer.
In a further aspect of the present invention, a connector is provided to receive the TAB lead connected to the contact pad to establish electrical connection therebetween. In a further aspect of the present invention, a conductive bump is provided between the TAB lead connected to the contact pad and the PCB pad to establish electrical connection thereamong. In a further aspect of the present invention, a conductive polymer is provided between the TAB lead connected to the contact pad and the PCB pad to establish electrical connection thereamong.
In a further aspect of the present invention, the interconnection and packaging of the contact structure is established through a bonding wire between the contact pad on the contact substrate and a contact target. In a further aspect of the present invention, the interconnection and packaging of the contact structure is established through a single layer TAB lead extending between the contact pad on the contact substrate and a contact target. In a further aspect of the present invention, the interconnection and packaging of the contact structure is established through a double layer TAB lead extending between the contact pad on the contact substrate and a contact target. In a further aspect of the present invention, the interconnection and packaging of the contact structure is established through a triple layer TAB lead extending between the contact pad on the contact substrate and a contact target.
According to the present invention, the packaging and interconnection has a very high frequency bandwidth to meet the test requirements in the next generation semiconductor test technology. The packaging and interconnection is able to mount the contact structure on a probe card or equivalent thereof by electrically connecting therewith through the bottom surface of the contact substrate mounting the contact structure. Moreover, because of the relatively small number of overall components to be assembled, the interconnection and packaging of the present invention can be fabricated with low cost and high reliability as well as high productivity.